In electronic circuits, digital signals are commonly converted to analog signals using digital-to-analog converters. Conventional digital-to-analog converters, sometimes referred to as "static" digital-to-analog converters, receive and process digital input data using discrete hardware components to generate an analog signal that represents the digital input data. The voltage level of the analog signal varies according to the digital input signal. For example, a two (2) bit static digital-to-analog converter with a voltage range of zero (0) to five (5) volts, provides an analog output of zero (0) to five (5) volts in increments of 1.25 volts, based upon the value of the two (2) bit input word. As the number of bits in the digital input word is increased, the size of the analog increments decrease. One of the problems with static digital-to-analog converters is that the discrete hardware components require a relatively large amount of space and consume a relatively large amount of power, making them unsuitable for applications that require compact, integrated solutions, such as personal communications services (PCS) devices.
One alternative to a static digital-to-analog converter is a so-called "digital-based" digital-to-analog converter. In general, digital-based digital-to-analog converters require relatively less power and space than their static digital-to-analog counterparts, making digital based converters particularly well suited for small, integrated applications. Two approaches used in digital-based digital-to-analog converters are pulse width modulation (PWM) and pulse density modulation (PDM).
As is well known in the art, PWM involves processing an N-bit input value to generate an analog signal with a voltage level that is proportional to the N-bit input value. A typical PWM modulator includes an N-bit counter, an N-bit comparator and a filter. The N-bit input value is applied to one of the comparator inputs. The output of the counter is applied to the other comparator input. The comparator compares the magnitude of the N-bit input value to the magnitude of the continuously counting counter output to generate a single bit periodic digital signal.
Characteristically, the duty cycle of the single bit periodic digital signal is proportional to the N-bit input value. Consider a three bit example, where the N-bit input value is three bits, the counter is a three bit counter and the comparator is a three bit comparator. For a single modulation cycle, the counter will count from "000" to "111". For a three bit input value of "001", the output of the three bit comparator is "11000000", which is continuously repeated. An output of "1" represents a logic HIGH and a "0" represents a logic LOW. For an input value of "110", the output of the three bit comparator is "11111110". Thus, the pulse width for the input value of "001" is two bits, while the pulse width for the input value of "110" is seven bits. The comparator output is applied to the filter to average the discrete levels of the single bit digital signal to produce a constant analog signal. The duty cycle of the single bit digital signal determines the value of the resulting analog signal.
A characteristic of PWM that presents some practical difficulties is that all of the logic HIGHs and LOWs ("1"s and "0"s) are contiguous within a modulation cycle. This characteristic is represented in the analog output as an AC component, which is often referred to as "ripple", typically expressed as a percentage of the logic HIGH voltage level. Ideally, the analog output is a constant DC value. However, because of the contiguous nature of the logic HIGHs and LOWs in the analog output, the analog output of a PWM modulator often contains AC ripple. The cutoff frequency of the filter is often lowered to attenuate ripple. However, this requires increasing the time constant of the filter which can significantly increase the response time of the filter and in some cases cause instability in control loops, making it unsuitable for high speed applications.
PDM is similar to PWM except that the ripple in the analog output is characteristically lower than in a comparable PWM analog signal. The reduced ripple is attributable to the logic HIGHs being more evenly distributed within a counter cycle. For example, for a modulation cycle having three logic HIGHs and five logic LOWs, the logic HIGHs are typically spaced apart by the logic LOWs. One common approach for distributing the logic HIGHs more evenly involves providing the output of the counter in non-sequential bit order to the comparator, typically by connecting the most significant through least significant outputs of the counter to the least significant through most significant inputs, respectively, of the comparator.
Refer again to the previous example where, for a single cycle, the counter counts from "000" to "111". However, the non-sequential inputs to the comparator are: "000", "100", "010", "110", "001", "101", "011"and "111". For a three bit input value of "001", the output of the three bit comparator is "10001000", which is continuously repeated. For an input value of "100",the output of the three bit comparator is "11101010". Thus, the logic HIGHs are more evenly distributed across a single cycle which, when processed by a filter, provide an analog output with a reduced AC component.
Although the PDM approach provides improved performance over the PWM approach, it has disadvantages. One of the problems with the PDM approach is that as the size of the input words increases, the time constant of the filter must be increased, causing a slower filter response. This problem can be particularly acute in applications that require large input words but also small integrated solutions, such as cellular telephony.
Accordingly, based upon the need to convert digital input values to analog signals in circuits and the limitations in prior approaches, an approach for performing digital-to-analog conversion that supports relatively large input words while providing relatively low ripple is highly desirable.